The present invention relates to a technique effectively applicable particularly to a semiconductor integrated circuit having metal insulator semiconductor field effect transistors (hereinafter abbreviated to "MISFETs").
A semiconductor integrated circuit of a high degree of integration employs an n-channel MISFET of a lightly doped drain (hereinafter abbreviated to "LDD") structure. The MISFET of an LDD structure has a drain region of low impurity concentration formed between a drain region of high impurity concentration and a channel forming region (that is, between a drain region of high impurity concentration and the region beneath the gate electrode of the MISFET). The drain region of low impurity concentration is formed integrally with the drain region having a high impurity density. It is an ordinary practice to form a lightly doped region by introducing an n-type impurity into the region through an ion implanting process using a gate electrode as a mask. The drain region of high impurity concentration is formed by introducing an n-type impurity into the region through an ion implantation process using a side wall insulating film selectively formed over the side walls of a gate electrode as a mask. The side wall insulating film can selectively be formed by forming a silicon oxide film over the side walls of a gate electrode through a chemical vapor deposition (hereinafter abbreviated to "CVD") process, and etching the silicon oxide film through an anisotropic etching process such as a reactive ion etching (hereinafter abbreviated to "RIE") process.
In a MISFET of such an LDD structure, the electric field intensity near the drain region can be reduced by reducing the impurity concentration gradient at the pn junction between the drain region and the channel forming region. That is, an MISFET of an LDD structure is featured by a capability of suppressing the generation of hot carriers and preventing the time-dependent deterioration of the threshold electrode. Furthermore, since an MISFET of an LDD structure has a portion having a low impurity density in the drain region, the diffusion of the drain region into the channel forming region is suppressed, and thereby an effective channel length is secured. That is, the MISFET of an LDD construction is featured by the capability of reducing the channel length while preventing the short channel effect.
A semiconductor integrated circuit having a complementary MOSFET (CMOS) is optimal for increasing operating speed and for reducing power consumption. To reduce the manufacturing process steps, in the CMOS of an LDD structure a side wall insulating film is formed over the side walls of the respective ate electrodes of the n-channel MISFET and the p-channel MISFET. In one technique, the p-channel MISFET, similarly to the n-channel MISFET, is formed in an LDD structure by providing a lightly doped region. Alternatively, the p-channel MISFET, while using a side wall insulating film, is provided without providing any lightly doped region. A side wall insulating film is formed also over the side walls of the gate electrode of a p-channel MISFET not formed in an LDD structure.
The CMOS of an LDD construction is published, for example, in International Electron Devices Meeting, Technical Digest, pp. 59-62, 1985, and U.S. Pat. No. 4,577,391.